PCIMX6QP5AVT2AB datasheet(80/166 Pages) NXP

80 / 166 page

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.12.4

Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)

AC Timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing.

4.12.4.1

SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 39 depicts the timing of SD/eMMC4.3, and Table 50 lists the SD/eMMC4.3 timing characteristics.

Figure 39.

SD/eMMC4.3 Timing

Table 50.

SD/eMMC4.3 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP

0400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

eSDHC Output/Card Inputs SD_CMD, SD_DATAx (Reference to SDx_CLK)

SD6

eSDHC Output Delay

tOD

–6.6

3.6

SD1

SD3

SD5

SD4

SD7

SDx_CLK

SD2

SD8

SD6

Output from uSDHC to card

Input from card to uSDHC

SDx_DATA[7:0]

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