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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCIMX6DP5AVT2AB 데이터시트(PDF) 49 Page - NXP Semiconductors |
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PCIMX6DP5AVT2AB 데이터시트(HTML) 49 Page - NXP Semiconductors |
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49 / 166 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 NXP Semiconductors 49 4.8 Output Buffer Impedance Parameters This section defines the I/O impedance parameters of the i.MX 6DualPlus/6QuadPlus processors for the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes •LVDS I/O •MLB I/O NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 9). |
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