Networking Clock Synthesizer and Zero Delay Buffer

MDS 680-01 F

6

Revision 020305

Integrated Circuit Systems, Inc.

ICS680-01

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70

° C

Note 1: Measured with a 15 pF load.

Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%.

Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

X1

25

MHz

ICLK

33

MHz

Output Frequency

Q0 to Q3, QFB, Note 1

33

MHz

Output Rise Time

20% to 80%, Note 1

1.5

ns

Output Fall Time

80% to 20%, Note 1

1.5

ns

Output Clock Duty Cycle

at VDD/2, Note 2

40

60

%

Power-up Time

PLL lock-time from

power-up to 1% of final

frequency

10

ms

PDTS goes high until

stable CLK outputs at

1% of final frequency

2ms

One Sigma Clock Period Jitter

Configuration

dependent

50

ps

Maximum Absolute Jitter

Deviation from mean.

Configuration

dependent.

±200

ps

QFB to ICLK Skew

Measured at VDD/2,

Note 3

-350

350

Pin-to-pin Skew

QFB, Q0 to Q3, Note 3

-250

250

ps