4

AMD-751™ System Controller Revision Guide

22564B-1—February 2000

Preliminary Information

1

Invalid Read Performed After a Slave PCI Target Abort

Products Affected. C3 and C5

Description. When the AMD-751 system controller initiates an unaligned doubleword PCI I/O read

transaction and this I/O read receives a target abort from the PCI slave, the next PCI I/O read returns

incorrect data. Aligned transactions are unaffected.

Potential Effect on System. A target abort on the PCI bus is an extremely rare event and the occurrence of

the abort is considered a catastrophic error condition. This condition was artificially created for PCI

testing and has not been observed in normal system validation testing.

Suggested Workaround. None

Resolution Status. Fixed in a future revision of the AMD-751 system controller.

2

Arbitration Latency Due to No Bus Preemption

Products Affected. C3

Description. The AMD-751 PCI arbiter can impose long latencies on external PCI bus masters when any

master that currently owns the bus is attempting long transfers due to not correctly supporting bus

preemption. When a PCI master’s bus grant is active and another master requests the bus, the arbiter

should immediately deassert the grant to the first master, thus preempting the first master. The first

master is permitted to continue bus transactions for the duration of its master latency timer. Due to

the anomaly in the arbiter, the original master does not get preempted if it owns the bus and it

continues to keep its request pin asserted. Therefore, it could use the bus indefinitely. However, this

problem has not been seen with any real system hardware and software.

Potential Effect on System. Some peripherals may experience timeouts. A lack of fairness on the bus.

Suggested Workaround. None

Resolution Status. Fixed in Rev C5.