AT90USB646 datasheet(39/434 Pages) ATMEL

39 / 434 page

7593A–AVR–02/06

AT90USB64/128

6.1.4

Asynchronous Timer Clock – clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows

using this Timer/Counter as a real-time counter even when the device is in sleep mode.

6.1.5

ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.1.6

USB Clock – clkUSB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL

running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock regis-

ter should be programmed by software to generate a 2MHz clock on the PLL input.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

6.2.1

Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-

grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out

period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that

all users can make their desired clock source setting using any available programming interface.

6.2.2

Clock Startup Sequence

Any clock source needs a sufficient V

CC to start oscillating and a minimum number of oscillating

cycles before it can be considered stable.

To ensure sufficient V

CC, the device issues an internal reset with a time-out delay (tTOUT) after

the device reset is released by all other reset sources. “On-chip Debug System” on page 57

describes the start conditions for the internal reset. The delay (t

TOUT) is timed from the Watchdog

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage

Table 6-1.

Device Clocking Options Select

(1)

Device Clocking Option

CKSEL3..0

Low Power Crystal Oscillator

1111 - 1000

Reserved

0111 - 0110

Low Frequency Crystal Oscillator

0101 - 0100

Internal 128 kHz RC Oscillator

0011

Calibrated Internal RC Oscillator

0010

External Clock

0000

Reserved

0001

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