35

Ω, SPST/SPDT, +3V

Logic-Compatible Analog Switches

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9

Applications Information

Power-Supply

Sequencing-Free Operation

Most CMOS switches require specific power-supply

sequencing in order to prevent device latchup. The

older DG417/DG418/DG419 devices require a proper

it is necessary to add signal diodes to the circuit in

order to prevent potential latchups. The new

DG417L/DG418L/DG419L devices eliminate the need

not exceed the absolute maximum ratings because

stresses beyond the listed ratings may cause perma-

nent damage to the devices.

+3V

0

LOGIC

INPUT

V-

300

Ω

GND

NO

COM

NC

V+

35pF

+10V

IN

V+

V-

LOGIC

INPUT

DG419L

Figure 4. Charge Injection

GND

NC OR

NO

1nF

V-

V-

V+

N.C.

IN

OFF

ON

OFF

Q =

COM

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

DG417L

DG418L

DG419L

V+

Figure 3. DG419L Break-Before-Make Interval

______________________________________Test Circuits/Timing Diagrams (continued)