STE2007DIE2 datasheet(18/62 Pages) STMICROELECTRONICS

18 / 62 page

4 INTERFACE

STE2007

18/62

Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper

electrical contact on VDD can be noted from a too low level of VLCD.

The serial interface Driver TxData–mode is controlled by three input signals.

The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled

when !CS is low after having received one Reading Command.

To access Driver TxData–mode a Reading command must be sent to STE2007 driver. The first

bit (D/C) is low to indicates next 8–bits are for command. The data is read to the driver on the

rising edge of SCLK (see section ”MCU TxData–mode”). After last command bit (bit 0) is read

SDAOUT becomes active (Low impedance) and MCU is able to read data from driver.

SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising

edges from the last SCLK rising edge of teh reading command transfer (Figure 8).

After sending out all 8 bits the driver release automatically the bus and go back to the MCU

TxData–mode. MCU Txdata line changes from high–z to active low or high in the falling edge of

8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue.

If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and

SDAOUT is forced in high impedance Mode.

SDAOUT and SDAIN line can be short circuited in normal working conditions.

Figure 8.

AC timing characteristics

Hi±Z

Status

Command

Hi±Z

SCLK

Hi±Z

Timing B

Timing A

Timing B

!CS

MCU TxData

Driver TxData

SCLK

Driver TxData

MCU TxData

MCU Data direction

Driver TxData

MCU TxData

Driver SDA direction

out

Driver SDA direction

D/C

1/2 SCLK

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