13

NXP Semiconductors

CD1020

Figure 4. Glitch filter and interrupt delay timers

SPI interface (continued)

SCLK low time

• Figure 6 - 5

56

—

—

ns

MOSI input setup time

• Figure 6 - 6

16

—

—

ns

MOSI input hold time

• Figure 6 - 7

20

—

—

ns

MISO access time

• Figure 6 - 8

—

—

116

ns

MISO disable time (21)

• Figure 6 - 9

—

—

100

ns

MISO output valid time

• Figure 6 - 10

—

—

116

ns

MISO output hold time (no cap on MISO)

• Figure 6 - 11

20

—

—

ns

Rise time

• Figure 6 - 12

—

—

30

ns

(21)

Fall time

• Figure 6 - 13

—

—

30

ns

(21)

CS_B negated time

• Figure 6 - 14

500

—

—

ns

WAKE-UP

LPM mode wake-up time triggered by edge of CS_B

—

755

1000

µs

(23)

Notes

21.

Guaranteed by characterization.

22.

the difference between the first and second channel selected as the multiplexed analog output. See Figure 8 for a typical AMUX access time VS

voltage step waveform.

23.

The parameter is guaranteed at VBATP = 6.0 V to 28 V.

Table 7. Dynamic electrical characteristics (continued)

100 pF load on MISO, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Units

Notes

LPM CLK

SG_Pin

Input Glitch

filter timer

INT_B

500ns