ZLP12840 datasheet(33/58 Pages) ZILOG

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PS024406-0106

P R E L I M I N A R Y

Port 0 Register

ZLP12840 OTP MCU

Product Specification

Port 0 Register

The Port 0 Register allows read and write access to the Port 0 pins. See Table 11.

Only P00, P01, and P07 are available on Crimzon ZLP12840 MCU 20-pin configura-

tions.

Table 11. Port 0 Register (P0)

Bit

Field

P07

P06

P05

P04

P03

P02

P01

P00

Reset

XXXXX

R/W

Address

Bank 03: 00h; Linear: 000h

Bit

Position R/W

Description

[7]

Read:

Write:

Port 0 Pin 7Available for I/O if UART Tx is disabled.

(Pin configured as input or output in P01M register.)

Pin level is Low.

Pin level is High.

(Pin configured as output in P01M register, UCTL[7]=0.)

Assert pin Low.

Assert pin High if configured as push-pull; make pin high-impedance if it is open drain.

[6:0]

Read:

Write:

Port 0 Pins 60Each bit provides access to the corresponding Port 0 pin.

(Pin configured as input or output in P01M register.)

Pin level is Low.

Pin level is High.

(Pin configured as output in P01M register.)

Assert pin Low.

Assert pin High if configured as push-pull; make pin high-impedance if it is open drain.

Note:

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