PD70224 datasheet(17/30 Pages) MICROCHIP

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Number

Pin Name

(PD70210A)

Pin Name

(PD70210)

Description

SUPP_S2

Input pin for sensing the voltage on the diode bridge

connected to the data pairs. This pin, along with the

SUPP_S1 pin, can be used to distinguish between 2-pair

and 4-pair operation for PSEs that operate in 4-pairs but

do not generate the classification procedure on both

pairs, but one pair only. Signal is referenced to VPN_IN.

Place a 10 KΩ resistor in the input of this pin.

RREF

Bias current resistor. A 60.4 KΩ 1 % resistor is connected

between RREF and IC ground (VPN_IN).

RCLS

Sets the class of the PD. Connect RCLASS (programming

resistor) between this pin and IC ground (VPN_IN).

Allowed values are 133 Ω, 69.8 Ω, 45.3 Ω, and 30.9 Ω for

Class 1, 2, 3, and 4, respectively. If RCLASS is not

present, the PD will draw up to 3 mA during classification,

indicating Class 0 (default type 1) to the PSE. Signal is

referenced to VPN_IN.

7,8

VPN_IN

Lower rail of the incoming PSE voltage rail, from the

negative terminal of the two OR-ed bridge rectifiers. The

corresponding upper PoE rail is VPP.

9,10

VPN_OUT

In effect, the switched ground for establishing continuity to

the PWM section after successful detection, classification,

and power-up. It is connected to the power ground and

PWM controller IC’s ground plane of the DC–DC

converter section.

AT_FLAG

Open drain output. This pin gets actively pulled low when

a type 2 PD-PSE mutually identifies each other through

classification. In PD70210A, there is a minimum 80 ms

delay from the moment that the input capacitor is fully

charged to this signal activity. In PD70210, this flag

asserts once inrush current is ended. Signal is referenced

to VPN_OUT.

HD_FLAG

Open drain output. This pin gets actively pulled low when

a 2-pair HDBaseT PD-PSE mutually identifies each other

through classification. In PD70210A, there is a minimum

80 ms delay from the moment that the input capacitor is

fully charged to this signal activity. In PD70210, this flag

asserts once inrush current is ended. Signal is referenced

to VPN_OUT.

4P_AT_FLAG

Open drain output. This pin gets actively pulled low when

a 4-pair version of a (non-standard) type 2 PD-PSE

mutually identifies each other through classification. In

PD70210A, there is a minimum 80 ms delay from the

moment that the input capacitor is fully charged to this

signal activity. In PD70210, this flag asserts once inrush

current is ended. Signal is referenced to VPN_OUT.

PD70210/PD70210A/PD70210AL

Pin Descriptions

Datasheet

DS00003695A-page 17

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