56F8335 datasheet(39/160 Pages) FREESCALE

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Interrupt Vector Table

56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

TMRA

0-2

P:$80

Timer A, Channel 0

TMRA

0-2

P:$82

Timer A, Channel 1

TMRA

0-2

P:$84

Timer A,Channel 2

TMRA

0-2

P:$86

Timer A, Channel 3

SCI0

0-2

P:$88

SCI 0 Transmitter Empty

SCI0

0-2

P:$8A

SCI 0 Transmitter Idle

Reserved

SCI0

0-2

P:$8E

SCI 0 Receiver Error

SCI0

0-2

P:$90

SCI 0 Receiver Full

ADCB

0-2

P:$92

ADC B Conversion Compete / End of Scan

ADCA

0-2

P:$94

ADC A Conversion Complete / End of Scan

ADCB

0-2

P:$96

ADC B Zero Crossing or Limit Error

ADCA

0-2

P:$98

ADC A Zero Crossing or Limit Error

PWMB

0-2

P:$9A

Reload PWM B

PWMA

0-2

P:$9C

Reload PWM A

PWMB

0-2

P:$9E

PWM B Fault

PWMA

0-2

P:$A0

PWM A Fault

core

- 1

P:$A2

SW Interrupt LP

1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced

from the vector table, providing only 19 bits of address.

2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are

the chip reset addresses; therefore, these locations are not interrupt vectors.

Table 4-5 Interrupt Vector Table Contents1 (Continued)

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

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