| 전자부품 데이터시트 검색엔진 |
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INA826 데이터시트(PDF) 25 Page - Texas Instruments |
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INA826 데이터시트(HTML) 25 Page - Texas Instruments |
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25 / 33 page ![]() 11.2 Layout Example Use ground pours for shielding the input signal pairs 1 RG 8 RG 2 –IN 7 +VS 3 +IN 6 OUT 4 –VS 5 REF R1 R2 C1 C2 GND GND +V –IN +IN OUT Input traces routed adjacent to each other – V R3 Ground plane removed at gain resistor to minimize parasitic capacitance Low-impedance connection for reference terminal Place bypass capacitors as close to IC as possible R3 +IN –IN +V OUT –V R1 R2 C1 C2 RG INA823 RG GND Figure 11-1. Example Schematic and Associated PCB Layout www.ti.com INA823 SBOSA75A – JULY 2021 – REVISED JULY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: INA823 |
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