MPC8548EEC datasheet(85/151 Pages) NXP

85 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Serial RapidIO

For each baud rate at which an LP-serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown

in Figure 52 with the parameters specified in Table 65 when measured at the output pins of the device and

the device is driving a 100-

Ω ± 5% differential resistive load. The output eye pattern of an LP-serial

Table 63. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Output voltage

–0.40

2.30

Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage

VDIFFPP

800

1600

mVp-p

—

Deterministic jitter

—

0.17

UI p-p

—

Total jitter

—

0.35

UI p-p

—

Multiple output skew

SMO

—

1000

Skew at the transmitter output between lanes of a

multilane link

Unit interval

400

±100 ppm

Table 64. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Output voltage

–0.40

2.30

Voltage relative to COMMON of either signal

comprising a differential pair

Differential output voltage

VDIFFPP

800

1600

mVp-p

—

Deterministic jitter

—

0.17

UI p-p

—

Total jitter

—

0.35

UI p-p

—

Multiple output skew

SMO

—

1000

Skew at the transmitter output between lanes of a

multilane link

Unit interval

320

±100 ppm

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