FEDL2240DIGEST-02

OKI Semiconductor

ML2240 Family

14/24

To read the channel status, input “L” level to

CS and RD pins. D0 pin will output the channel status in

synchronization with SCK clock.

The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined

by the level at SCK pin at the falling edge of

CS pin.

The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7.

Status Read Timing

• SCK Rising Edge Operation

• SCK Falling Edge Operation

DO (O)

CS (I)

RD (I)

D7

SCK (I)

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Hi-Z

DO (O)

CS (I)

RD (I)

D7

SCK (I)

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Hi-Z