MPC8544EBVTARGA datasheet(96/117 Pages) NXP

96 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Thermal

19.6.2

Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed. Refer to Section 4.4,

“Platform to FIFO Restrictions,” for additional information.

20 Thermal

This section describes the thermal specifications of the MPC8544E.

20.1

Thermal Characteristics

Table 70 provides the package thermal characteristics.

Table 69. FIFO Maximum Speed Restrictions

Platform Speed (MHz)

Maximum FIFO Speed for Reference Clocks TSECn_TX_CLK, TSECn_RX_CLK

(MHz)1

533

126

400

Note:

1. FIFO speed should be less than 24% of the platform speed.

Table 70. Package Thermal Characteristics

Characteristic

JEDEC Board

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection

Single layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient natural convection

Four layer board (2s2p)

RθJA

°C/W

1, 2

Junction-to-ambient (@200 ft/min)

Single layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient (@200 ft/min)

Four layer board (2s2p)

RθJA

°C/W

1, 2

Junction-to-board thermal

—

RθJB

°C/W

Junction-to-case thermal

—

RθJC

<0.1

°C/W

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL

SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1

°C/W.

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