ADP1052ACPZ-R7 datasheet(96/113 Pages) AD

96 / 113 page

ADP1052

Data Sheet

Rev. B | Page 96 of 113

Figure 67 and Register 0xFE3C in Table 159 describe the modulation limit settings.

tRX

tFX

tRY

tFY

t0, START OF

SWITCHING CYCLE

tS/2

tS, END OF

SWITCHING CYCLE

tS/2

OUTx

tMODU_LIMIT

Figure 67. Setting Modulation Limits

Table 159. Register 0xFE3C—Modulation Limit

Bits

Bit Name/Function

R/W

Description

[7:0]

Modulation limit

R/W

This register sets the modulation limit, tMODU_LIMIT (maximum duty cycle). The modulation limit is the

maximum time variation for the modulated edges from the default timing (see Figure 67). The step

size of an LSB depends on the switching frequency.

Switching Frequency Range (kHz)

LSB Step Size (ns)

49 to 87

97.5 to 184

195.5 to 379

390.5 to 625

Table 160. Register 0xFE3D—Feedforward and Soft Start Filter Gain

Bits

Bit Name/Function

R/W

Description

Soft start enable of open-loop

input voltage feedforward

operation

R/W

Setting this bit enables the soft start procedure of the open-loop input voltage

feedforward operation. If this function is used, set Bit 6.

Open-loop input voltage

feedforward operation enable

R/W

0 = open-loop input voltage feedforward operation is disabled.

1 = open-loop input voltage feedforward operation is enabled.

High frequency ADC debounce time

R/W

This bit sets the debounce time for detecting the settling of the VS high frequency

ADC. Bit 4 must be set to 1 to enable this function.

0 = 5 ms debounce time.

1 = 10 ms debounce time.

High frequency ADC debounce

enable

R/W

Setting this bit enables a debounce time for detecting the settling of the VS high frequency

ADC at the end of a soft start. The debounce time is set using Bit 5.

Feedforward ADC selection

R/W

Always set this bit to select the 11-bit VF ADC (factory default setting).

Feedforward enable

R/W

This bit enables or disables feedforward control during closed-loop operation.

0 = closed-loop input voltage feedforward control is disabled.

1 = closed-loop input voltage feedforward control is enabled.

[1:0]

Soft start filter gain

R/W

These bits set the soft start gain of the soft start filter.

Bit 1

Bit 0

Soft Start Filter Gain

ADP1052ACPZ-R7 데이터시트(PDF) 96 Page - Analog Devices

ADP1052ACPZ-R7 데이터시트(HTML) 96 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL