ADP5056ACCZ-R7 datasheet(30/31 Pages) AD

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ADP5056

Data Sheet

Rev. 0 | Page 30 of 31

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Optimal circuit board layout is essential to obtain the best

performance from the ADP5056 (see Figure 50). Poor layout

can affect the regulation and stability of the device, as well as

the EMI and electromagnetic compatibility (EMC) performance.

Refer to the following guidelines for an optimal PCB layout:



Place the input capacitor, inductor, output capacitor, and

bootstrap capacitor near to the IC.



Use short, thick traces to connect the input capacitors to

the PVINx pins, and use dedicated power ground to connect

the input and output capacitor grounds to minimize the

connection length.



Use several high current vias, if required, to connect PVINx

and PGND to other power planes.



Use short, thick traces to connect the inductors to the SWx

pins and the output capacitors.



Ensure that the high current loop traces are as short and

wide as possible.



Maximize the amount of ground metal connecting Pin 35,

Pin 36, and Pin 37, and use as many vias as possible on the

component side to improve thermal dissipation.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.



Place the decoupling capacitors near to the VREG pin and

VBIAS pin.



Place the frequency setting resistor near to the RT pin.



Place the feedback resistor divider near to the FBx pin. In

addition, keep the FBx traces away from the high current

traces and the switch node to avoid noise pickup.



Use size 0402 or 0603 resistors and capacitors to achieve

the smallest possible footprint solution on boards where

space is limited.

For recommended PCB assembly and manufacturing

procedures, visit the μModule® design and manufacturing

resources page.

Figure 50. Typical PCB Layout for the ADP5056

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