EDBA164B4PK-1DATF-R datasheet(9/152 Pages) MICRON

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LPDDR2 Array Configuration

The 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic

random-access memory containing 4,294,967,296-bits. The device is internally config-

ured as an eight-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as

16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is or-

ganized as 16,384 rows by 1024 columns by 32 bits.

General Notes

Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-

preted as any or all DQ collectively, unless specifically stated otherwise.

“DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively,

unless specifically stated otherwise. “BA” includes all BA pins used for a given density.

Complete functionality may be described throughout the entire document. Any page or

diagram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

Any specific requirement takes precedence over a general statement.

Any functionality not specifically stated herein is considered undefined, illegal, is not

supported, and will result in unknown operation.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

LPDDR2 Array Configuration

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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