DMA2286 datasheet(18/48 Pages) MICRONAS

18 / 48 page

DMA 2275, DMA 2286

Table 8–3, continued

Address

Label

Bit No.

Function

209

PSL

PSH

0–7

8–15

packet 0 syndrom low byte

packet 0 syndrom high byte

PSL + PSH = 0:

packet 0 received without error

PSL + PSH > 0:

packet 0 received with error

210

PDL

PDH

0–7

8–15

packet 0 data low byte

packet 0 data high byte

8.3. DRAM Interface

The data transfer between descrambler chip and acqui-

sition DRAM interface controlled by the FP. The external

64 k x 1 bit DRAM has to store the following data

streams:

– line 625

28 byte/40ms

→

5600 bit/s

– packet bus

2 x 96 byte/448

µs → 3430000 bit/s

– IM bus

→ 500000 bit/s

The 1 bit DRAM interface offers a maximum data rate of

5.0625 Mbit/s by using four 20.25 MHz cycles for one

page mode read or write access. A 150 ns DRAM fulfills

the access time requirements. Fig. 9–14 shows the

DRAM interface waveform. Refresh of the DRAM is con-

trolled by the FP, which starts a number of refresh cycles

within every line. An 8 bit refresh is performed to allow

the use of 256 Kbit DRAMs.

The acquisition DRAM is used on one side to store re-

ceived packet data and line 625 information needed by

the CCU and the conditional access subsystem (CASS)

and on the other side to store control information needed

by the descrambler chip (e.g. control words, filter coeffi-

cients, packet addresses etc.). Therefore, the descram-

bler chip does not include special IM bus registers ex-

cept those for subaddressing and sound processing (on

the DMA 2286 only).

The upper end of the DRAM address space can be used

as a scratch buffer for the CCU software. This DRAM

area is also refreshed and will never be used by the des-

crambler chip.

DMA2286 데이터시트(PDF) 18 Page - Micronas

DMA2286 데이터시트(HTML) 18 Page - Micronas

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

데이터시트 다운로드

링크 URL