CONFIDENTIAL ADVANCE INFORMATION Rev. 0.71

April 6, 2015

ES9023 Datasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

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FUNCTIONAL DESCRIPTION

I

Run by the I

If a smaller bit-width is used, the remaining is ‘zero-padded’. Driving the DIF pin low will set the DAC in I

driving the pin high will set the DAC in LJ mode. Below is a timing diagram illustrating the two modes (LJ and I

the ES9023.

Zero Detect

The zero-detect function outputs an external status signal (ZD) based on a zero-valued input for a given number of clock

cycles. The ZD output signal is set high when both data channels are zero for 8192 LRCK cycles.

MCLK

Asynchronous mode: MCLK must be > 192 x fs.

Synchronous mode: Please see table below for supported configurations.

LRCK (kHz)

MCLK (MHz)

fs

128 x fs

192 x fs

256 x fs

384 x fs

512 x fs

768 x fs

1152 x fs

32

-

-

-

12.288

16.384

24.576

36.864

44.1

-

-

11.2896

16.9344

22.5792

33.8688

-

48

-

-

12.288

18.432

24.576

36.864

-

88.2

11.2896

16.9344

22.5792

33.8688

45.1584

-

-

96

12.288

18.432

24.576

36.864

49.152

-

-

176.4

22.5792

33.8688

45.1584

-

-

-

-

192

24.576

36.864

49.152

-

-

-

-

For best performance, 256 x fs or greater is recommended for 32kHz to 96kHz sampling.