ES9026PRO datasheet(34/57 Pages) ESS

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CONFIDENTIAL ADVANCE INFORMATION v3.4

March 5, 2019

ES9026PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Bits

[7:6]

[5:4]

[3:2]

[1:0]

Mnemonic

adc_first_orderb

adc_clk_sel

adc_dither_enb

adc_pdb

Default

2’b00

Bit

Mnemonic

Description

[7:6]

adc_first_orderb

Selects whether the ADC uses a first-order modulator or a second-

order modulator in the analog section.

[7] affects ADC2 while [6] is reserved.

•

1’b0: uses a first order modulator providing the best

performance (default)

•

1’b1: uses a second order modulator

[5:4]

adc_clk_sel

Sets the clock dividing ratio for the ADC analog section.

This setting also affects the decimation filter stages.

•

2’d0: ADC_CLK = MCLK

•

2’d1: ADC_CLK = MCLK/2

•

2’d2: ADC_CLK = MCLK/4

•

2’d3: ADC_CLK = MCLK/8

[3:2]

adc_dither_enb

Allows the ADC dither to be disabled on a per ADC basis.

[3] affects ADC2 while [2] is reserved.

•

1’b0: uses TPDF shaped dither providing the best

performance (default)

•

1’b1: disabled dither

[1:0]

adc_pdb

Shuts down each ADC independently.

[1] affects ADC2 while [0] is reserved.

Note: GPIO must be configured as ADC mode for the ADC to

function correctly.

•

1’b0: shuts down the ADC (default)

•

1’b1: enables the ADC analog stage

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