ES9038Q2M datasheet(7/65 Pages) ESS

7 / 65 page

July 17, 2019

CONFIDENTIAL Rev. 1.3

ES9038Q2M Datasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

Master Mode

The DAC can become an audio timing master via master_mode in Register 10: Master Mode and Sync Configuration.

The ‘input_select’ bits in Register 1: Input selection must be set to explicitly select DSD or serial master mode.

Autoselect will not produce the desired results in master mode.

The Bit Clock frequency can be configured using one of the following two methods:

Set the desired master_div in Register 10: Master Mode and Sync Configuration, or

Use NCO mode to set FSR using Register 34-37: Programmable NCO. When in NCO mode the master_div setting will be

ignored.

An available GPIO pin can be configured to output MCLK using Register 8: GPIO1-2 Configuration.

DATA_CLK

DATA1

DATA2

SIN (Serial PCM Data)

DATA_CLK

DATA1

DATA2

GPIO1/2

MCLK (Master Clock)

SLAVE PCM MODE

MASTER PCM MODE

BCLK (Bit Clock)

LRCLK (Frame Clock)

BCLK (Bit Clock)

LRCLK (Frame Clock)

SIN (Serial PCM Data)

DATA_CLK

DATA1

DATA2

DSD DATA2 (R)

DATA_CLK

DATA1

DATA2

GPIO1/2

MCLK (Master Clock)

SLAVE DSD MODE

MASTER DSD MODE

DSD DATA_CLK

DSD DATA1 (L)

DSD DATA2 (R)

DSD DATA_CLK

DSD DATA1 (L)

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