Layout recommendations

STSPIN840

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DocID031835 Rev 1

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Layout recommendations

The STSPIN840 device integrates the power stage; in order to improve the thermal

dissipation, the exposed pad must be connected to the ground plane on the bottom layer

using multiple vias equally spaced. This ground plane acts as a heatsink, for this reason it

should be as wide as possible.

in order to reject high frequency noise components on the supply. A bulk capacitor could

also be required (typically a 33

F). The connection between the power supply connector

In order to ensure the best ground connection between the STSPIN840 and the other

components, a GND plane surrounding the device is recommended.

A capacitor between REF pins and ground should be positioned as near as possible to the

device in order to filter the noise and stabilize the reference voltage.

Several vias should be positioned as near as possible each sense resistor connecting them

to the ground plane on the bottom layer. In this way, both the GND planes provide a path for

the current flowing into the power stage.

The path between the ground of the shunt resistors and the ceramic bypass capacitor of the

device is critical; for this reason it must be as short as possible minimizing parasitic

inductances that can cause voltage spikes on SENSE and OUT pins.

The OUT pins and the VS nets can be routed using the bottom layer, it is recommended to

use two vias for output connections.

Figure 15. PCB layout example (top layer)