Also included are two EXTSEL and EXTCLK pins to allow

testing the chip via an external source The EXTSEL pin

once set to high

causes the External-Clock

Mux to

change its input from the output of the VCO and Counter to

the external clock signal provided via EXTCLK input pin

CLK1SEL pin changes the output frequency of the

CLK1

0 CLK1

6 outputs During normal operation when

CLK1SEL pin is high these outputs are at the same fre-

quency as the input crystal oscillator while CLK2 and CLK4

outputs are at twice and four times the input frequency re-

spectively

Once CLK1SEL pin is set to a low logic level the CLK1

outputs will be at twice the input frequency the same as the

CLK2 output with CLK4 output still being at four times the

input frequency

In addition two other pins are added for increasing the test

capability SKWSEL and SKWTST pins allow testing of the

counter’s output and skew of the output drivers by bypass-

ing the VCO In this test mode CLK4 frequency is the same

as SKWTST input frequency while CLK2 is

and CLK1

frequencies are

respectively (refer to the truth table) In

addition CLK1SEL functionality is also true under this test

condition

Typical Application

TLF11955 – 3

Block Diagram

CGS700

TLF11955 – 2

Truth Table

Input

Output

CLK1

EXT

EXT

SKW

SKW

TRI-STATE

CLK4

CLK2

CLK1

SEL

SEL

CLK

SEL

TST

HL

X

L

X

H

LL

X

L

X

H

XH

XX

H

HL

X

H

c

c

LL

X

H

c

c

XX

X

X

X

L

Z

Z

Z

Steady State phase frequency lock

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