DLPC4430 datasheet(36/49 Pages) TI

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10 Layout

10.1 Layout Guidelines

To achieve the needed thermal connectivity, 2-ounce copper planes in the PCB design are recommended .

10.1.1 PCB Layout Guidelines for Internal DLPC4430 Power

The following guidelines to achieve desired controller performance relative to internal PLLs are recommended:

• The DLPC4430 controller contains four PLLs (PLLM1, PLLM2, PLLD and PLLS), each of which have a

dedicated 1.15V digital supply, and three (PLLM1, PLLM2 and PLLD) which have a dedicated 1.8-V analog

supply. It is important to have filtering on the supply pins that covers a broad frequency range. Each 1.15V

PLL supply pin must have individual high frequency filtering in the form of a ferrite bead and a 0.1µF ceramic

capacitor. These components must be located very close to the individual PLL supply balls. The impedance

of the ferrite bead must be greater than that of the capacitor at frequencies above 10MHz. The 1.15V to the

PLL supply pins must also have low frequency filtering in the form of an RC filter. This filter can be common

to all the PLLs. The voltage drop across the resistor is limited by the 1.15V regulator tolerance and the

DLPC4430 device voltage tolerance. A resistance of 0.36 Ω and a 100 µF ceramic are recommended.

• The analog 1.8V PLL power pins must have a similar filter topology as the 1.15V. In addition, it is

recommended that the 1.8V be generated with a dedicated linear regulator.

• When designing the overall supply filter network, care must be taken to ensure no resonance occurs.

Particular care must be taken around the 1 to 2MHz band, as this coincides with the PLL natural loop

frequency.

DLPC4430

DLPS223 – DECEMBER 2021

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DLPC4430 데이터시트(PDF) 36 Page - Texas Instruments