VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8166

2.488 Gbit/sec

1:16 SONET/SDH Demux with Clock Recovery

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

G52252-0, Rev 3.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/9/99

Figure 4: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

High Speed Interface

The incoming 2.488Gb/s data is received by high speed inputs DI+. The data inputs are internally termi-

nated by a center-tapped resistor network. For differential input DC coupling, the network is terminated to the

capacitor.

In most situations these inputs will have high transition density and little DC offset. However, in cases

where this does not hold, direct DC connection is possible. Serial data inputs have the circuit topology shown in

Figure 5. The reference voltage is created by a resistor divider as shown. If the input signal is driven differen-

tially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this refer-

ence voltage and not exceed the maximum allowable amplitude (

operations, it is recommended that the user provides an external reference voltage which has better temperature

and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal

value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either

side of the differential gate.

VSC8166

0.1uF

50

Ω

50

Ω

0.1uF

downstream

bias point

generated

internally