AL4CS241 datasheet(9/25 Pages) ETC1

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AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251

December 14, 2001

8.1.2 DATA OUTPUTS (Q8-Q0)

Q8 ~ Q0 are 9-bit wide of output data port.

8.2 Controls

8.2.1 Reset (/RS)

Reset takes place when the Reset (/RS) input is LOW. During reset, both internal read and write

pointers are set to the staring position. A reset is required to initial internal logic after power-up. The

Full Flag (/FF) and Programmable Almost-Full Flag (/PAF) will be reset to HIGH after tRSF. The

Empty Flag (/EF) and Programmable Almost-Empty Flag (/PAE) will be reset to LOW after tRSF.

During reset, the output register is initialized to all zeros and the offset registers are initialized to their

default values.

8.2.2 Write Clock (WCLK)

A write cycle is initiated on the rising edge of the Write Clock (WCLK). Data setup and hold times

must be met with respect to the rising edge of WCLK. The Full Flag (/FF) and Programmable Almost-

Full Flag (/PAF) are synchronized with respect to the rising edge of the Write Clock (WCLK).

The Write and Read Clocks can be asynchronous or coincident.

8.2.3 Write Enable1 (/WEN1)

If the FIFO is configured to support programmable flags, Write Enable 1 (/WEN1) is the only enable

control pin. In this configuration, when Write Enable 1 (/WEN1) is low, data can be written into the

input register and memory array on the rising edge of every Write Clock (WCLK). Data is stored in

the memory array sequentially and independently of any on going read operation. When Write Enable

1 (/WEN1) is HIGH, the input holds the previous data and no new data can be written into the

memory array. If the FIFO is configured to have two write enables, which allows for depth expansion,

two enable control pins are involved in the write operations. Please refer Write Enable 2 (WEN2)

section for details. To prevent data overflow, the Full Flag (/FF) will go LOW, inhibiting further write

operations. Upon the completion of a valid read cycle, the Full Flag (/FF) will go HIGH after tWFF,

allowing a valid write to begin. Write Enable(s) are ignored when the FIFO is full.

8.2.4 Read Clock (RCLK)

Data can be read on the outputs on the rising edge of the Read Clock (RCLK), when all the output

controls /REN1, /REN2, Output Enable (/OE) are set LOW. The Empty Flag (/EF) and

Programmable Almost-Empty Flag (/PAE) are synchronized with respect to the rising edge of the

Read Clock (RCLK). The Write and Read Clocks can be asynchronous or coincident.

8.2.5 Read Enable (/REN1, /REN2)

When both Read Enables (/REN1, /REN2) are LOW, data is read from the memory array to the

output register on the rising edge of the Read Clock (RCLK). When either Read Enable (/REN1,

/REN2) is HIGH, the output register holds the previous data and no new data can to be loaded into

the register. When all the data has been read from the FIFO, the Empty Flag (/EF) will go LOW,

inhibiting further read operations. Once a valid write operation has been done, the Empty Flag (/EF)

will go HIGH after tREF and a valid read can begin. The Read Enables (/REN1, /REN2) are ignored

when the FIFO is empty.

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