SN74HCS74 datasheet(13/32 Pages) TI

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9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure

optimal performance. This can be accomplished by providing short, appropriately sized traces from the

SN74HCS74-Q1 to the receiving device(s).

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

Circuit response without RC debounce

Vin := CLK input, Vout := Q output illustrates an example of a single button press bouncing and causing the

output to toggle multiple times. This will cause issues in the desired application. Circuit response with RC

debounce

Vin := CLK input, Vout := Q output illustrates 4 button presses with an added debounce circuit, fixing the

unwanted toggling and allowing for proper toggle switch operation.

Time (100 Ps/div)

D001

Vout

Vin

Figure 9-2. Circuit response without RC debounce

Vin := CLK input, Vout := Q output

Time (200 ms/div)

D002

Vout

Vin

Figure 9-3. Circuit response with RC debounce

Vin := CLK input, Vout := Q output

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SN74HCS74-Q1

SCES894E – APRIL 2019 – REVISED DECEMBER 2021

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SN74HCS74 데이터시트(PDF) 13 Page - Texas Instruments