PCF8545ATT datasheet(13/54 Pages) NXP

13 / 54 page

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

13 of 54

NXP Semiconductors

PCA8576F

Automotive 40 × 4 LCD driver

7.3.4 RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two

successive display RAM columns of four rows (see Figure 8).

7.3.5 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 5. After each byte is stored, the content of the data pointer

is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminates early then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.3.6 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0 and A1. The subaddress counter value is defined by

the device-select command (see Table 9). If the content of the subaddress counter and

the hardware subaddress do not match then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

Fig 8.

Display RAM filling order in 1:4 multiplex drive mode

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