PCF8545ATT datasheet(8/48 Pages) NXP

8 / 48 page

PCE85176AUG

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 12 January 2015

8 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

7.2.4 Blinking

The display blinking capabilities of the PCE85176AUG are very versatile. The whole

display can blink at frequencies selected by the blink-select command (see Table 16). The

blink frequencies are derived from the clock frequency. The ratio between the clock and

blink frequencies depends on the selected blink mode (see Table 17).

An additional feature is for an arbitrary selection of LCD elements to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD elements can blink by selectively changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 8).

[1]

The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see

Table 25.

7.3 Display RAM

The display RAM is a static 40

 4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

Table 17.

Blink frequencies

Blink mode

Blink frequency[1]

off

blink

clk

768

----------

blink

clk

1536

-------------

blink

clk

3072

-------------

PCF8545ATT 데이터시트(PDF) 8 Page - NXP Semiconductors

PCF8545ATT 데이터시트(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

데이터시트 다운로드

링크 URL