SN74HCS245 datasheet(13/23 Pages) TI

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9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure

optimal performance. This can be accomplished by providing short, appropriately sized traces from the

SN74HCS245 to one or more of the receiving devices.

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in MΩ; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

Time (ns)

100

-2

3.3

-1

Figure 9-2. Simulated signal integrity at the reciever with different damping resistor (Rd) values

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SN74HCS245

SCLS879 – JANUARY 2022

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