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REF35102 데이터시트(PDF) 21 Page - Texas Instruments |
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REF35102 데이터시트(HTML) 21 Page - Texas Instruments |
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21 / 27 page ![]() 12 Layout 12.1 Layout Guidelines Figure 12-1 illustrates an example of a PCB layout for a data acquisition system using the REF35. Some key considerations are: • Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF of the REF35. • Decouple other active devices in the system per the device specifications. • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. Figure 12-2 illustrates pin compatibility with TI REF30xx, REF31xx and REF33xx series references in SOT23-3 package when using REF35xxx family footprint. Key is to rotate the REF30xx, REF31xx and REF33xx reference devices by 180º before assembly. 12.2 Layout Example Not to scale VREF NR VIN GND GND EN 1 2 3 6 5 4 C C Optional C Figure 12-1. Layout Example Not to scale REF35 REF30 REF31 REF33 VREF OUT (Pin 2) NR VIN IN (Pin 1) GND GND (Pin 3) GND EN 1 2 3 6 5 4 C C Optional C Figure 12-2. Pin Compatibility with REF30xx, REF31xx and REF33xx www.ti.com REF35 SNAS809 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: REF35 |
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