STM32MP157D datasheet(45/261 Pages) STMICROELECTRONICS

45 / 261 page

DS12504 Rev 6

45/261

STM32MP157A/D

Functional overview

3.33

Hash processors (HASH1, HASH2)

The devices embed two processors that support the advanced algorithms usually required

to ensure authentication, data integrity and non-repudiation when exchanging messages

with a peer:

•

Universal HASH

–

SHA-1, SHA224 and SHA256 (secure HASH algorithms)

–MD5

–HMAC

The accelerator supports DMA request generation.

HASH1 can be defined (in ETZPC) as accessible by secure software only.

3.34

Boot and security and OTP control (BSEC)

The BSEC (boot and security and OTP control) is intended to control an OTP (one time

programmable) fuse box, used for embedded non-volatile storage for device configuration

and security parameters. Some part of BSEC should be configured as accessible by secure

software only.

3.35

Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers, two basic

timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system

timers in each Cortex-A7.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose, basic and low-

power timers.

Table 4. Timer feature comparison

Timer

type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Comple-

mentary

output

Max

interface

clock

(MHz)

Max

timer

clock

(MHz)(1)

Advanced

-control

TIM1,

TIM8

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes

104.5

209

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