DSC2133 datasheet(2/16 Pages) MICROCHIP

2 / 16 page

DSC2133/DSC2233

DS20006231A-page 2



2022 Microchip Technology Inc. and its subsidiaries

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Input Voltage, VIN..............................................................................................................................–0.3V to VDD + 0.3V

Supply Voltage .......................................................................................................................................... –0.3V to +4.0V

ESD Protection On All Pins ......................................................................... 400V MM, 4000V HBM, 1500V CDM (max.)

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Note:

1000+ years of data retention on internal memory.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Supply Voltage (Note 1)

VDD

2.25

—

3.6

—

Supply Current (Note 2)

IDD

—

EN pin low – outputs are

disabled

—

EN pin high – outputs are

enabled; RL=100Ω,

fO1 = fO2 = 156.25 MHz

Frequency Stability

f

—

±25

ppm

Includes frequency variations

due to initial tolerance, temp.

and power supply voltage.

±50

Aging

f

—

±5

ppm

1 year @ 25°C

Startup Time (Note 3)

tSU

—

T = 25°C

Input Logic Levels

VIH

0.75VDD

—

Input logic high

VIL

—

0.25VDD

Input logic low

Output Disable Time

(Note 4)

tDA

—

Output Enable Time

tEN

—

Pull-up Resistor (Note 2)

—

k

Pull-up resistor exists on all

digital IO

LVDS Output

Output Offset Voltage

—

1.125

—

1.4

R = 100Ω differential

Delta Offset Voltage

—

Peak-to-Peak Output

Swing

—

350

—

Single-ended

Output Transition Time

(Note 4)

tr/tf

—

200

—

20% to 80%

RL = 50Ω, CL = 2 pF

Note 1: Pin 4 VDD should be filtered with 0.01 µf capacitor.

2: Output is enabled if Enable pad is floated or not connected.

3: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.

4: Output Waveform and Test Circuit figures define the parameters.

5: Period Jitter includes crosstalk from adjacent output.

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