SPC58EE80E7 datasheet(66/154 Pages) STMICROELECTRONICS

66 / 154 page

Electrical characteristics

SPC58EEx, SPC58NEx

66/154

DS11646 Rev 4

3.12.5

SD ADC filter modes

15. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the

different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The

time elapsed between data availability at pin and internal S/D module registers is given by the below formula:

of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK is the frequency of the peripheral

bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1

clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be

added by the target module (core, DMA, interrupt) controller to process the data received from the ADC S/D module.

16. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

17. Consumption is given after power-up, when steady state is reached. Extra consumption up to 2 mA may be required during

internal circuitry set-up.

Table 30. Digital output codes in full scale

OSR

MCR[GECEN] = 1

31081

31077

31079

31075

31026

31040

31081

31077

31079

31075

31128

31026

31040

31081

112

31078

128

31079

144

31076

160

31026

176

31040

192

31081

224

31078

256

31079

512

31079

1024

31079

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