| 전자부품 데이터시트 검색엔진 |
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SR2 데이터시트(PDF) 6 Page - STMicroelectronics |
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SR2 데이터시트(HTML) 6 Page - STMicroelectronics |
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6 / 22 page ![]() Pin descriptions SR2 6/22 DocID026047 Rev 2 2 Pin descriptions 2.1 Power supply (VCC) This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the SR2 device as possible. 2.2 Ground (VSS) Ground pin for the device. 2.3 Smart Reset™ input (SR0) Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST). By connecting a voltage higher than VCC to the SR0 the device enters a test mode (see Section 1: Description on page 3 for more information). 2.4 Smart Reset™ input (SR1) Push-button Smart Reset™ input is active low with optional pull-up resistor. Both SR inputs need to be asserted simultaneously for at least tSRC to assert the reset output (RST). 2.5 Reset output (RST) RST is active low or active high, push-pull or open drain reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to deassert); Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset™ input state. If VCC drops below 1.575 V, the RST output is deasserted and its state is guaranteed down to 1 V (see Figure 8). |
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