ST25DV04K datasheet(71/200 Pages) STMICROELECTRONICS

71 / 200 page

Figure 29. Read mode sequences

Dev sel *

Byte addr

Dev sel

Data out 1

Data out N

Current address read

Dev sel

Data out

Random address read

Dev sel *

Data out

Sequential current read

Data out N

Dev sel *

Byte addr

Sequential random read

Dev sel *

Data out1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

6.5.3

Sequential Read access

This operation can be used after a Current Address Read or a Random Address Read. The bus master does

acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the

next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and

must generate a Stop condition, as shown in Figure 29. Read mode sequences.

The output data comes from consecutive addresses, with the internal address counter automatically incremented

after each byte output.

Sequential read in user memory:

•

Sequential read cannot cross area borders. After reaching area border, device continues to output FFh

•

There is no roll over inside area or at the end of user memory (ST25DVxxx returns only FFh after last user

memory byte address).

Sequential read in system memory:

•

There is no roll over after reaching end of system memory (ST25DVxxx returns only FFh after last system

memory byte address).

•

Sequential read in dynamic registers:

•

It is possible to read sequentially dynamic registers and fast transfer mode’s mailbox (contiguous I2C

addresses).

ST25DV04K ST25DV16K ST25DV64K

I2C read operations

DS10925 - Rev 9

page 71/200

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