STA369BWS_V01 datasheet(84/92 Pages) STMICROELECTRONICS

84 / 92 page

STA369BWS

84/92

DocID016861 Rev 7

7.23.6

Description

Root part number 1 implements an automatic CRC computation for the Biquad and

MDRC / XOver coefficient memory (Table 72). RAM memory cell contents from address

0x00 to 0x27 are bit XORed to obtain BQCHKE checksum, while cells from 0x28 to 0x31 are

XORed to obtain the XCCHKE checksum. Both checksum (24-bit wide) are exported on I2C

registers from 0x60 to 0x65. The checksum computation starts as soon as the BCGO (for

biquad RAM bank) or the XCGO bits (for MDRC / XOver coefficients) are set to 1. The

checksum is computed at the processing sample rate if IR bits equal to 01 or 10, otherwise

the checksum is computed to half processing sample rate.

When BCCMP or XCCMP are set to 1 the relative checksum (BQCHKE and XCCHKE) is

continuously compared with BQCHKR and XCCHKR respectively. If the checksum match

with its own reference value, the respective result bits (BCRES and XCRES) are set to 0.

The compare bits have no effect if the respective GO bit is not set.

In case of checksum errors (that is, the internally computed didn’t match the reference), an

automatic device reset action can be activated. This function is enabled when BCAUTO or

XCAUTO bits are set to ‘1’. The automatic reset bits have no effect if the respective

compare bits are not set.

The suggested procedure for Automatic reset activation is the following one:

Download coefficients set (RAM locations 0x00…0x27)

Download externally computed biquad checksum into registers BQCHKR

Enable checksum of biquad coefficients by setting BCGO bit. Checksum starts to be

automatically computed by Root part number 1 and its value written in registers

BQCHKE.

Enable checksum comparison by setting BCCMP bit. Internally computed checksum

will start to be compared with the reference one and result will be exposed on the

BCRES bit. Following operation will be executed on each audio frame:

if (BQCHKE == BQCHKR)

{

BC_RES = 0;

}

// Checksum is ok, reset the error bit

else

{

BC_RES = 1;

}

// Checksum error detected, set the error bit

Wait until the BCRES bit goes to 0, meaning checksum result bit has started to be

updated and everything is ok. Time out for this operation (for example, >1 ms) indicates

checksum failure, MCU will handle this event.

Enable automatic reset of the device in case of checksum error by setting the BCAUTO

bit. The BCRES bit will then be automatically checked by STA369BWS, on each audio

frame, and reset event will be triggered in case of checksum mismatch.

Periodically check BCRES status. A value of 1 indicates a checksum mismatch has

occurred and, therefore, the device went through a reset cycle.

The previous example is intended for biquad CRC bank calculations, but it can be easily

extended to MDRC / XOver CRC computation.

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