STA369BWS datasheet(78/92 Pages) STMICROELECTRONICS

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STA369BWS

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7.20

Miscellaneous registers (addr 0x4B, 0x4C)

7.20.1

MISC1 (addr 0x4B)

Rate powerdown enable (RPDNEN) bit

In Root part number 1, by default, powerdown pin and I2C powerdown act on mute

commands to perform the fadeout. This default can be changed so that the fadeout can be

started using master volume. RPDNEN bit, when set, activates this feature.

Noise shaping on DC-cut filter enable (NSHHPEN) bit

Following what described in Section 7.18, this bit, when set, enables the noise shaping

technique on DC-cut filter. Channels 1 and 2 share the same settings.

Bridge immediate off (BRIDGOFF) bit

A fadeout procedure is started in Root part number 1, once PWDN function is enabled and

after 13 million clock cycles (PLL internal frequency) the bridge is put in powerdown

(Tristate mode). There is also the possibility to change this behavior so that the power

bridge is switched off immediately after PWDN pin is tied to ground, without, therefore

waiting for the 13 million clock cycles. BRIDGOFF bit, when set, activates this function.

Obviously, the immediate powerdown generates a pop noise at the output, hence this

procedure must be used only in cases where pop noise is not relevant in the application.

Note that this feature works only for hardware PWDN assertion and not for a power down

applied through I2C interface. Refer to Section : Power down delay selector (PNDLSL[2:0])

bits on page 81 when it is necessary to program a different number of clock cycles.

F3X™ mode activation (F3X) bits

F3X™ technology allows the PWM carrier to be suppressed for the auxiliary outputs. When

activated, pins 17, 18, 19 and 20 are the channel outputs that can be connected as per

figure Figure 25 below. This circuit suppresses the PWM carrier fundamental and its

harmonics by low-pass filtering the stereo signal. Typical resistor and capacitor values are

given for filtering the PWM signal.

Note:

F3X mode works only with binary modulation. See Section : Binary output enable registers

on page 52 for how to select this configuration.

RPDNEN

NSHHPEN

BRIDGOFF

F3XEN[1]

F3XEN[0]

CPWMEN

Reserved

BOOST

00000100

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