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STA369BWSTR 데이터시트(PDF) 18 Page - STMicroelectronics

부품명 STA369BWSTR
상세설명  2.1-channel 40-watt high-efficiency digital audio system Sound Terminal®
PDF  92 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STA369BWSTR 데이터시트(HTML) 18 Page - STMicroelectronics

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Serial audio interface
STA369BWS
18/92
DocID016861 Rev 7
4
Serial audio interface
The STA369BWS audio serial input interface was designed to interface with standard digital
audio components and to accept a number of serial data formats. The STA369BWS always
acts as the slave when receiving audio input from standard digital audio components. Serial
data for two channels is provided using three inputs: left/right clock LRCKI, serial clock
BICKI, and serial data SDI12.
The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial
data format is I2S, MSB-first.
4.0.1
Timings
In the STA369BWS the BICKI and LRCKI pins are configured as inputs and they must be
supplied by the external peripheral.
Figure 6. Timing diagram for SAI interface
4.0.2
Delay serial clock enable
To tolerate anomalies in some I2S master devices, a PLL clock cycle delay can be added to
the BICKI signal before the SAI interface.
4.0.3
Channel input mapping
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
Table 8. Timing parameters for slave mode
Symbol Parameter
Min
Typ
Max
Unit
tBCy
BICK cycle time
80
-
-
ns
tBCH
BICK pulse width high
40
-
-
ns
tBCL
BICK pulse width low
40
-
-
ns
tLRSU
LRCKI setup time to BICKI strobing edge
40
-
-
ns
tLRH
LRCKI hold time to BICKI strobing edge
40
-
-
ns
tLRJT
LRCKI Jitter Tolerance
40
ns



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