STM32F107RC datasheet(55/108 Pages) STMICROELECTRONICS

55 / 108 page

DocID15274 Rev 10

55/108

STM32F105xx, STM32F107xx

Electrical characteristics

107

A device reset allows normal operations to be resumed.

The test results are given in Table 31. They are based on the EMS levels and classes

defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

•

Unexpected reset

•

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC61967-2 standard which specifies the test board and the pin loading.

Table 31. EMS characteristics

Symbol

Parameter

Conditions

Level/

Class

VFESD

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

VDD = 3.3 V, LQFP100, TA =

+25 °C, fHCLK = 72 MHz, conforms

to IEC 61000-4-2

VEFTB

Fast transient voltage burst limits to be

applied through 100 pF on VDD and VSS

pins to induce a functional disturbance

VDD = 3.3 V, LQFP100, TA =

+25 °C, fHCLK = 72 MHz, conforms

to IEC 61000-4-4

STM32F107RC 데이터시트(PDF) 55 Page - STMicroelectronics

STM32F107RC 데이터시트(HTML) 55 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL