SIRC16DP datasheet(2/9 Pages) VISHAY

2 / 9 page

SiRC16DP

www.vishay.com

Vishay Siliconix

S17-0667-Rev. C, 08-May-17

Document Number: 77722

For technical questions, contact: pmostechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Notes

a. Package limited

b. Surface mounted on 1" x 1" FR4 board

c. t = 10 s

d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper

(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not

required to ensure adequate bottom side solder interconnection

e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components

f. Maximum under steady state conditions is 65 °C/W

g. TC = 25 °C

Notes

a. Pulse test; pulse width

 300 μs, duty cycle  2 %

b. Guaranteed by design, not subject to production testing

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE RATINGS

PARAMETER

SYMBOL

TYPICAL

MAXIMUM

UNIT

Maximum junction-to-ambient b, f

 10 s

RthJA

°C/W

Maximum junction-to-case (drain)

Steady state

RthJC

1.8

2.3

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Static

Drain-source breakdown voltage

VDS

VGS = 0 V, ID = 250 μA

Gate-source threshold voltage

VGS(th)

VDS = VGS, ID = 250 μA

2.4

Gate-source leakage

IGSS

VDS = 0 V, VGS = +20 V, -16 V

± 100

Zero gate voltage drain current

IDSS

VDS = 25 V, VGS = 0 V

0.06

0.10

VDS = 25 V, VGS = 0 V, TJ = 70 °C

On-state drain current a

ID(on)

VDS  5 V, VGS = 10 V

Drain-source on-state resistance a

RDS(on)

VGS = 10 V, ID = 15 A

0.00080

0.00096



VGS = 4.5 V, ID = 10 A

0.00110

0.00140

Forward transconductance a

gfs

VDS = 10 V, ID = 15 A

Dynamic b

Input capacitance

Ciss

VDS = 10 V, VGS = 0 V, f = 1 MHz

5150

Output capacitance

Coss

1950

Reverse transfer capacitance

Crss

350

Crss/Ciss ratio

0.068

0.140

Total gate charge

VDS = 10 V, VGS = 10 V, ID = 10 A

105

VDS = 10 V, VGS = 4.5 V, ID = 10 A

-31.5

Gate-source charge

Qgs

-12.1-

Gate-drain charge

Qgd

-5.6

Gate resistance

f = 1 MHz

0.1

0.5

0.9



Turn-on delay time

td(on)

VDD = 10 V, RL = 1 , ID  10 A,

VGEN = 10 V, Rg = 1 

-13

Rise time

-21

Turn-off delay time

td(off)

-35

Fall time

-9

Turn-on delay time

td(on)

VDD = 10 V, RL = 1 , ID  10 A,

VGEN = 4.5 V, Rg = 1 

-26

Rise time

-36

Turn-off delay time

td(off)

-31

Fall time

-12

Drain-source Body Diode Characteristics

Continuous source-drain diode current

TC = 25°C

Pulse diode forward current

ISM

100

Body diode voltage

VSD

IS = 5 A, VGS = 0 V

0.41

0.55

Body diode reverse recovery time

trr

IF = 10 A, di/dt = 100 A/μs,

TJ = 25 °C

-46

Body diode reverse recovery charge

Qrr

-47

Reverse recovery fall time

-21-

Reverse recovery rise time

-25-

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