PCF8545ATTAY datasheet(30/68 Pages) NXP

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NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

Display RAM addresses (columns)/segment outputs (S)

013aaa454

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

S0 S1 S2 S3 S4

S35 S36 S37 S38 S39

Multiplex 1:8 drive mode

Multiplex 1:6 drive mode

Multiplex 1:4 drive mode

S0 S1 S2 S3 S4

S35 S36 S37 S38 S39 S40 S41

BP0

BP1

BP2

BP3

BP4

BP5

BP0

BP1

BP2

BP3

S0 S1 S2 S3 S4

S35 S36 S37 S38 S39 S40 S41 S42 S43

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs and between the bits in a RAM row and the backplane outputs.

Figure 19. Display RAM bitmap

Logic 1 in the RAM bit map indicates the on-state (Von(RMS)) of the corresponding LCD

element; similarly, logic 0 indicates the off-state (Voff(RMS)). For more information on

Von(RMS) and Voff(RMS), see Section 7.4.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements,

• the RAM columns and the segment outputs,

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 19, shows row 0 to row 7 and column 0 to column 43.

Row 0 to row 7 correspond with the backplane outputs BP0 to BP7. Column 0 to column

43 correspond with the segment outputs S0 to S43. In multiplexed LCD applications,

the data of each row of the display RAM is time-multiplexed with the corresponding

backplane (row 0 with BP0, row 1 with BP1, and so on).

When display data is transmitted to the PCF8545, the display bytes received are stored

in the display RAM in accordance with the selected LCD multiplex drive mode. The data

PCF8545

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 4 October 2021

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