LM9823CCWM datasheet(6/22 Pages) NSC

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Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output

impedance of the sensor, prevents damage to the LM9823 from transients during power-up.

Note 8: To guarantee accuracy, it is required that VA and VD be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When

both VA and VD are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin.

Note 9: Typicals are at TJ=TA=25°C, fMCLK = 12MHz, and represent most likely parametric norm.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer

function of the AFE.

Note 12: The sensor’s maximum peak differential signal range is defined as the peak sensor output voltage for a white (full scale) image, with respect to the dark reference

level.

Note 13:

PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula

where

Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, DOE = 0, and a single OS input with a gain register setting of 1 (000001b) and

an offset register setting of 0 (000000b).

Note 15: The digital supply current (ID) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D7 - D0).

The current required to switch the digital data bus can be calculated from: ISW = 2*ND*PSW*CL*VD/tMCLK where ND is total number of data pins, PSW is the probability of

each data bit switching, CL is the capacitive loading on each data pin, VD is the digital supply voltage and tMCLK is the period of the MCLK input. For most applications, ND

is 8, PSW is ≈ 0.5, and VD is 5V, and the switching current can be calculated from: ISW = 40*CL/tMCLK. (With VD at 3.3V, the equation becomes: ISW = 26.4*CL/tMCLK.) For

example, if the capacitive load on each digital output pin (D7 - D0) is 20pF and the period of tMCLK is 1/12MHz or 83ns, then the digital switching current would be 9.6mA.

The calculated digital switching current will be drawn through the VD pin and should be considered as part of the total power budget for the LM9823.

Note 16: All specifications quoted in LSBs are based on 12 bit resolution.

OS Input

AGND

TO INTERNAL

CIRCUITRY

VWHITE

VREF

VRFT

CCD Output Signal

CIS Output Signal

VWHITE

Black Level

Gain

PGA

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



PGA code

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()32

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AC Electrical Characteristics (Continued)

LM9823CCWM 데이터시트(PDF) 6 Page - National Semiconductor (TI)

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