AD9213 datasheet(49/110 Pages) AD

49 / 110 page

Data Sheet

AD9213

Rev. A | Page 49 of 110

Figure 109 shows a simplified block diagram of the complex to real conversion.

LOW-PASS

FILTER

REAL

HB1 FIR

LOW-PASS

FILTER

HB1 FIR

COMPLEX TO

REAL ENABLE

90°

0°

–

COMPLEX TO REAL CONVERSION

GAIN STAGE

cos(wt)

sin(wt)

I/REAL

0dB

6dB

0dB

6dB

0dB

6dB

0dB

6dB

fS/4

Figure 109. Complex to Real Conversion Block

DDC EXAMPLE CONFIGURATIONS

Table 22 and Table 23 describes the register settings for multiple DDC example configurations, where bandwidths are with <−0.001 dB of

pass-band ripple and >100 dB of stop band alias rejection.

Table 22. Example DDC Configurations per ADC Channel Pair, Full Bandwidth Mode

Chip Application

Layer

Chip

Decimation

Ratio (DCM)

DDC

Output

Type

Bandwidth

Per DDC1

No. of Virtual

Converters

Required

Full Bandwidth Mode

Don’t care

50% × fS

0x606 = 0x00 (full bandwidth mode)

0x607 = 0x00 (chip decimate by 1)

0x630 = 0x00 (don’t care)

0x631 = 0x00 (don’t care)

1 fS is the ADC sample rate.

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