TMUX7348F datasheet(39/59 Pages) TI

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9.3.2.4 Overvoltage Protection and Detection

The TMUX7348F and TMUX7349F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with

the fault supplies (VFP and VFN). A signal is considered overvoltage if it exceeds the fault supply voltages by the

threshold voltage (VT).

When an overvoltage is detected, the switch automatically turns OFF regardless of the logic controls. The

source pin becomes high impedance and ensures only small leakage current flows through the switch and the

overvoltage does not appear on the drain. When the overvoltage channel is selected by the logic control, the

drain pin (D or Dx) is pulled to the supply that was exceeded. For example, if the source voltage exceeds VFP,

then the drain output is pulled to VFP. If the source voltage exceeds VFN, then the drain output is pulled to VFN.

The pull-up impedance is approximately 40 kΩ, and as a result, the drain current is limited to roughly 1 mA

during a shorted load (to GND) condition.

Figure 9-1 shows a detailed view of how the pullup or down controls the output state of the drain pin under a

fault scenario.

VDD

VSS

VFP

VFN

GND

ESD

Protection

Logic &

Fault

Detection

40 kΩ

Figure 9-1. Detailed Functional Diagram

VFP and VFN are required fault supplies that set the level at which the overvoltage protection is engaged. VFP can

be supplied from 3 V to VDD, while the VFN can be supplied from VSS to 0 V. If the fault supplies are not available

in the system, the VFP pin must be connected to VDD, while the VFN pin must be connected to VSS. In this case,

overvoltage protection then engages at the primary supply voltages VDD and VSS.

9.3.2.5 Adjacent Channel Operation During Fault

When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,

and the drain pin will be pulled up or down as described in Section 9.3.2.4. During such an event, all other

channels not under a fault can continue to operate as normal. For example, if S1 voltage exceeds VFP, and the

logic pins are set to S1, the drain output is pulled to VFP. Then if the logic pins are changed to set S4, which

is not in overvoltage or undervoltage, the drain will disconnect from the pullup to VFP and the S4 switch will be

enabled and connected to the drain, operating as normal. If the logic pins are switched back to S1, the S4 switch

will be disabled, the drain pin will be pulled up to VFP again, and the switch from S1 to drain will not be enabled

until the overvoltage fault is removed.

9.3.2.6 ESD Protection

All pins on the TMUX7348F and TMUX7349F support HBM ESD protection level up to ±3.5 kV, which helps the

device from getting ESD damages during the manufacturing process.

The drain pins (D or Dx) have internal ESD protection diodes to the fault supplies VFP and VFN. Therefore, the

voltage at the drain pins must not exceed the fault supply voltages to prevent excessive diode current. The

source pins have specialized ESD protection that allows the signal voltage to reach ±60 V regardless of the

supply voltage level. Exceeding ±60 V on any source input may damage the ESD protection circuitry on the

device and cause the device to malfunction if the damage is excessive.

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TMUX7348F

SCDS400 – MARCH 2022

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