Data Sheet

ADE1202

Rev. 0 | Page 33 of 42

REGISTER DETAILS

LOCK REGISTER

Address: 0x000, Reset: 0x0001, Name: LOCK

The user must write to the LOCK register to unlock the device before they can successfully write to any configuration register. The user

can always read registers even when the device is locked.

Table 18. Bit Descriptions for LOCK

Bits

Bit Name

Description

Reset

Access

[15:4]

LOCK_KEY

Lock Key. To reset or set the LOCK bit, write the LOCK_KEY = 0xADE. To unlock the device, write

0xADE0 to the LOCK register. To lock the device, write 0xADE1 to the LOCK register.

0x0

W

[3:1]

RESERVED

Reserved.

0x0

R

0

LOCK

Lock Bit. After reset, the device is locked with the LOCK bit set to 1. To configure the device, write

this bit to 0 and then write the desired configuration registers. After writing 1 to the LOCK bit,

normal operation resumes in about 100 µs. The lock function does not affect the ADDR_RELOAD bit,

the LOCK register, and the INT_STATUS register, which can all be written when LOCK = 1.

0x1

R/W

CONTROL REGISTER

Address: 0x001, Reset: 0x1080, Name: CTRL

The control register allows the user to change several operating modes and also read model and revision information.

Table 19. Bit Descriptions for CTRL

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

W

[13:12]

MODEL

Model Identifier.

0x0

R

0: reserved.

1: device is an ADE1202.

[11:9]

CHIP_ADDR

Chip Address. The CHIP_ADDR bit field is the chip address used by the SPI. The bit field

value is determined based on the voltage on the ADDR pin at power-up.

0x0

R

[8:5]

REVID

Version Identifier. The current revision of the integrated circuit is 0x4.

0x4

R

4

SW_RST

Software Reset. Write a 1 to the SW_RST bit to reset the device.

0x0

W

3

ADDR_RELOAD

Address Reload. Write a 1 to this bit to force the chip address to be decoded and

latched from the voltage on the ADDR pin.

0x0

W

2

IRQ_PIN_MODE

IRQ/DOUT2 Pin Mode.

0x0

R/W

0: the pin is assigned to DOUT2 and is in push/pull mode by default.

1: the pin is assigned to IRQ and is in open-drain mode.

1

RESERVED

Reserved.

0x0

R

0

SPI_CRC_APPEND_EN

SPI CRC Append Enable. If this bit is set when the user performs an SPI read and keeps

clocking for 16 cycles, a 16-bit CRC is appended to the read operation.

0x0

R/W