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ADF4252BCPZ-R7 데이터시트(PDF) 1 Page - Analog Devices |
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ADF4252BCPZ-R7 데이터시트(HTML) 1 Page - Analog Devices |
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1 / 30 page ![]() Dual Fractional-N/Integer-N Frequency Synthesizer Data Sheet ADF4252 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 3.0 GHz fractional-N/1.2 GHz integer-N 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage to 5 V Programmable dual modulus prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Programmable modulus on fractional-N synthesizer Trade off noise vs. spurious performance APPLICATIONS Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment GENERAL DESCRIPTION The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The RF synthesizer has a Σ-Δ-based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM ADF4252 2 DOUBLER OUTPUT MUX 4-BIT R COUNTER PHASE FREQUENCY DETECTOR LOCK DETECT CHARGE PUMP REFERENCE REFIN REFOUT VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET 24-BIT DATA REGISTER CLK DATA LE RFINA RFINB CPRF CPIF 2 DOUBLER CHARGE PUMP PHASE FREQUENCY DETECTOR MUXOUT AGND1 AGND2 DGND CPGND1 CPGND2 IFINB FRACTIONAL-N RF DIVIDER INTEGER-N IF DIVIDER IFINA 15-BIT R COUNTER Figure 1. |
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