| 전자부품 데이터시트 검색엔진 |
|
PPC5604BAVLL4R 데이터시트(PDF) 53 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PPC5604BAVLL4R 데이터시트(HTML) 53 Page - NXP Semiconductors |
|
53 / 109 page ![]() Package pinouts and signal descriptions MPC5604B/C Microcontroller Data Sheet, Rev. 15 NXP Semiconductors 53 Figure 11. VDD_HV and VDD_BV maximum slope When STANDBY mode is used, further constraints are applied to the both VDD_HV and VDD_BV in order to guarantee correct regulator function during STANDBY exit. This is described on Figure 12. STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY capacitance on application board (capacitance and ESR typical values), but would actually depend on exact characteristics of application external regulator. Figure 12. VDD_HV and VDD_BV supply constraints during STANDBY mode exit VDD_HV t d d VDD POWER UP POWER DOWN VDD_HV(MAX) FUNCTIONAL RANGE VDD_HV(MIN) VDD_HV VDD_HV(MIN) ΔVDD(STDBY) VDD_HV VDD_HV(MAX) VDD_LV t d d VDD STDBY () ΔVDD(STDBY) VDD_LV(NOMINAL) 0V |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |