ADIN1100CCPZ-R7 datasheet(70/78 Pages) AD

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Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

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Rev. 0 | 70 of 78

Table 114. Bit Descriptions for FC_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FC_EN

Frame Checker Enable. Set to 1 to enable the frame checker.

0x1

R/W

FRAME CHECKER INTERRUPT ENABLE REGISTER

Device Address: 0x1F; Register Address: 0x8004, Reset: 0x0001, Name: FC_IRQ_EN

This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame

checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.

The status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.

Table 115. Bit Descriptions for FC_IRQ_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FC_IRQ_EN

Frame Checker Interrupt Enable. When set, this bit enables the frame checker interrupt.

0x1

R/W

FRAME CHECKER TRANSMIT SELECT REGISTER

Device Address: 0x1F; Register Address: 0x8005, Reset: 0x0000, Name: FC_TX_SEL

This register is used to select the transmit side or receive side for frames to be checked. If set, frames received from the MAC interface to

be transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful

if remote loopback is enabled (see the MAC_IF_REM_LB_EN bit in the MAC_IF_LOOPBACK register) because it can be used to check the

received data after it is looped back at the MAC interface.

Table 116. Bit Descriptions for FC_TX_SEL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FC_TX_SEL

Frame Checker Transmit Select. When set, this bit indicates that the frame checker must check frames received to be

transmitted by the PHY.

0x0

R/W

1: check frames from the MAC interface to be transmitted by the PHY.

0: check frames received by the PHY from the remote end.

RECEIVE ERROR COUNT REGISTER

Device Address: 0x1F; Register Address: 0x8008, Reset: 0x0000, Name: RX_ERR_CNT

The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY.

Table 117. Bit Descriptions for RX_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

RX_ERR_CNT

Receive Error Count. This is the receive error counter associated with the frame checker in the PHY. Note that this

bit is self clearing upon reading.

0x0

R SC

FRAME CHECKER COUNT HIGH REGISTER

Device Address: 0x1F; Register Address: 0x8009, Reset: 0x0000, Name: FC_FRM_CNT_H

This register is a latched copy of Bits[31:16] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is

read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized.

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